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1 ? fn3082.4 ICL7106, icl7107, icl7107s 3 1 / 2 digit, lcd/led display, a/d converters the intersil ICL7106 and icl7107 are high performance, low power, 3 1 / 2 digit a/d converters. included are seven segment decoders, display driver s, a reference, and a clock. the ICL7106 is designed to interface with a liquid crystal display (lcd) and includes a multiplexed backplane drive; the icl7107 will directly drive an instrument size light emitting diode (led) display. the ICL7106 and icl7107 bring together a combination of high accuracy, versatility, and true economy. it features auto- zero to less than 10 v, zero drift of less than 1 v/ o c, input bias current of 10pa (max), and rollover error of less than one count. true differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. features ? guaranteed zero reading for 0v input on all scales ? true polarity at zero for precise null detection ? 1pa typical input current ? true differential input and refe rence, direct display drive - lcd ICL7106, led lcl7107 ? low noise - less than 15 v p-p ? on chip clock and reference ? low power dissipation - typically less than 10mw ? no additional active circuits required ? enhanced display stability ordering information part no. temp. range ( o c) package pkg. no. ICL7106cpl 0 to 70 40 ld pdip e40.6 ICL7106cm44 0 to 70 44 ld mqfp q44.10x10 icl7107cpl 0 to 70 40 ld pdip e40.6 icl7107rcpl 0 to 70 40 ld pdip (note) e40.6 icl7107scpl 0 to 70 40 ld pdip (note) e40.6 icl7107cm44 0 to 70 44 ld mqfp q44.10x10 note: ?r? indicates device with re versed leads for mounting to pc board underside. ?s? indicates enhanced stability. data sheet august 2002 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 pinouts ICL7106, icl7107 (pdip) top view icl7107r (pdip) top view ICL7106, icl7107 (mqfp) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 (1000) ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z buff int v- g2 (10?s) c3 a3 g3 bp/gnd (1?s) (10?s) (100?s) (minus) (100?s) 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 (1000) ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z buff int v- g2 (10?s) c3 a3 g3 bp/gnd (1?s) (10?s) (100?s) (minus) (100?s) osc 2 nc osc 3 test nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 osc 1 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 28 27 26 25 24 23 22 21 20 19 18 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol bp/gnd 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 in hi in lo a-z buff int v- nc g2 c3 a3 g3 ref hi ref lo c ref + c ref - common ICL7106, icl7107, icl7107s
3 absolute maximum rati ngs thermal information supply voltage ICL7106, v+ to v-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v icl7107, v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6v icl7107, v- to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9v analog input voltage (either input) (note 1) . . . . . . . . . . . . v+ to v- reference input voltage (either input). . . . . . . . . . . . . . . . . v+ to v- clock input ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test to v+ icl7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v+ operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 2) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (mqfp - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. input voltages may exceed the supply voltages provided the input current is limited to 100 a. 2. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications (note 3) parameter test conditions min typ max unit system performance zero input reading v in = 0.0v, full scale = 200mv -000.0 000.0 +000.0 digital reading stability (last digit) (ICL7106s, icl7107s only) fixed input voltage (note 6) -000.0 000.0 +000.0 digital reading ratiometric reading v ln = v ref , v ref = 100mv 999 999/10 00 1000 digital reading rollover error -v in = +v ln ? 200mv difference in reading for e qual positive and negative inputs near full scale - 0.2 1 counts linearity full scale = 200mv or full scale = 2v maximum deviation from best straight line fit (note 5) - 0.2 1 counts common mode rejection ratio v cm = 1v, v in = 0v, full scale = 200mv (note 5) - 50 - v/v noise v in = 0v, full scale = 200mv (peak-to-peak value not exceeded 95% of time) -15- v leakage current input v ln = 0 (note 5) - 1 10 pa zero reading drift v ln = 0, 0 o c to 70 o c (note 5) - 0.2 1 v/ o c scale factor temperature coefficient v in = 199mv, 0 o c to 70 o c , (ext. ref. 0ppm/ o c) (note 5) - 1 5 ppm/ o c end power supply character v+ supply current v in = 0 (does not include led current for icl7107) - 1.0 1.8 ma end power supply character v- supply current icl7107 only - 0.6 1.8 ma common pin analog common voltage 25k ? between common and positive supply (with respect to + supply) 2.4 3.0 3.2 v temperature coefficient of analog common 25k ? between common and positive supply (with respect to + supply) - 80 - ppm/ o c display driver ICL7106 only peak-to-peak segment drive voltage peak-to-peak backplane drive voltage v+ = to v- = 9v (note 4) 4 5.5 6 v ICL7106, icl7107, icl7107s
4 display driver icl7107 only segment sinking current v+ = 5v, segment voltage = 3v except pins 19 and 20 5 8 - ma pin 19 only 10 16 - ma pin 20 only 47 - ma notes: 3. unless otherwise noted, specifications apply to both the ICL7106 and icl7107 at t a = 25 o c, f clock = 48khz. ICL7106 is tested in the circuit of figure 1. icl7107 is tested in the circuit of figure 2. 4. back plane drive is in phase with segment drive for ?off? segment, 180 degrees out of phase for ?on? segment. frequency is 20 times conversion rate. average dc component is less than 50mv. 5. not tested, guaranteed by design. 6. sample tested. typical applications and test circuits figure 1. ICL7106 test circuit and typical application with lcd display components selected for 200mv full scale figure 2. icl7107 test circuit and typical application with led display components selected for 200mv full scale electrical specifications (note 3) (continued) parameter test conditions min typ max unit 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - com in hi in lo a-z buff int v- g2 c3 a3 g3 bp display display c 1 c 2 c 3 c 4 r 3 r 1 r 4 c 5 + - in r 5 r 2 9v ICL7106 c 1 = 0.1 f c 2 = 0.47 f c 3 = 0.22 f c 4 = 100pf c 5 = 0.02 f r 1 = 24k ? r 2 = 47k ? r 3 = 100k ? r 4 = 1k ? r 5 = 1m ? + - 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - com in hi in lo a-z buff int v- g2 c3 a3 g3 gnd display display c 1 c 2 c 3 c 4 r 3 r 1 r 4 c 5 + - in r 5 r 2 icl7107 +5v -5v c 1 = 0.1 f c 2 = 0.47 f c 3 = 0.22 f c 4 = 100pf c 5 = 0.02 f r 1 = 24k ? r 2 = 47k ? r 3 = 100k ? r 4 = 1k ? r 5 = 1m ? ICL7106, icl7107, icl7107s
5 typical integrator amplifie r output waveform (int pin) design information summary sheet ? oscillator frequency f osc = 0.45/rc c osc > 50pf; r osc > 50k ? f osc (typ) = 48khz ? oscillator period t osc = rc/0.45 ? integration clock frequency f clock = f osc /4 ? integration period t int = 1000 x (4/f osc ) ? 60/50hz rejection criterion t int /t 60hz or t lnt /t 60hz = integer ? optimum integration current i int = 4 a ? full scale analog input voltage v lnfs (typ) = 200mv or 2v ? integrate resistor ? integrate capacitor ? integrator output voltage swing ?v int maximum swing: (v- + 0.5v) < v int < (v+ - 0.5v), v int (typ) = 2v ? display count ? conversion cycle t cyc = t cl0ck x 4000 t cyc = t osc x 16,000 when f osc = 48khz; t cyc = 333ms ? common mode input voltage (v- + 1v) < v ln < (v+ - 0.5v) ? auto-zero capacitor 0.01 f < c az < 1 f ? reference capacitor 0.1 f < c ref < 1 f ?v com biased between vi and v-. ?v com ? v+ - 2.8v regulation lost when v+ to v- < ? 6.8v if v com is externally pulled down to (v+ to v-)/2, the v com circuit will turn off. ? ICL7106 power supply: single 9v v+ - v- = 9v digital supply is generated internally v gnd ? v+ - 4.5v ? ICL7106 display: lcd type: direct drive with digital logic supply amplitude. ? icl7107 power supply: dual 5.0v v+ = +5v to gnd v- = -5v to gnd digital logic and led driver supply v+ to gnd ? icl7107 display: led type: non-multiplexed common anode r int v infs i int ---------------- - = c int t int () i int () v int ------------------------------- - = v int t int () i int () c int ------------------------------- - = count 1000 v in v ref --------------- = auto zero phase (counts) 2999 - 1000 signal integrate phase fixed 1000 counts de-integrate phase 0 - 1999 counts total conversion time = 4000 x t clock = 16,000 x t osc ICL7106, icl7107, icl7107s
6 detailed description analog section figure 3 shows the analog section for the ICL7106 and icl7107. each measurement cycle is divided into three phases. they are (1) auto-zero (a-z), (2) signal integrate (int) and (3) de-integrate (de). auto-zero phase during auto-zero three things happen. first, input high and low are disconnected from the pins an d internally shorted to analog common. second, the reference capacitor is charged to the reference voltage. third, a feedback loop is closed around the system to charge the auto-zero capacitor c az to compensate for offset voltages in the buff er amplifier, integrator, and comparator. since the comparator is included in the loop, the a- z accuracy is limited only by the noise of the system. in any case, the offset referred to the input is less than 10 v. signal integrate phase during signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. the converter then integrates the differential voltage between in hi and in lo for a fixed time. this differential voltage can be within a wide common mode range: up to 1v from either supply. if, on the other hand, the input signal has no return with respect to the converter power supply, in lo can be tied to analog common to establish the correct common mode voltage. at the end of this phase, the polarity of the integrated signal is determined. de-integrate phase the final phase is de-integrate, or reference integrate. input low is internally connected to analog common and input high is connected across the pr eviously charged reference capacitor. circuitry within the ch ip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. the time required for the output to return to zero is proportional to the input signal. specifically the digital reading displayed is: . differential input the input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5v below the positive supply to 1v above the negative supply. in this range, the syst em has a cmrr of 86db typical. however, care must be exercised to assure the integrator output does not saturate. a worst case condition would be a large positive common mode volt age with a near full scale negative differential input voltage. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. for these critical applications the in tegrator output swing can be reduced to less than the recommended 2v full scale swing with little loss of accuracy. the integrator output can swing to within 0.3v of either supply without loss of linearity. differential reference the reference voltage can be generated anywhere within the power supply voltage of the converter. the main source of common mode error is a roll-over voltage caused by the reference capacitor losing or ga ining charge to stray capacity on its nodes. if there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. this difference in reference for positive or negative input voltage will give a roll-over error. however, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst ca se. (see component value selection.) display count = 1000 v in v ref --------------- ?? ?? ?? ICL7106, icl7107, icl7107s
7 analog common this pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating with respect to the power supply. the common pin sets a voltage that is approximately 2.8v more negative than the positive supply. this is selected to give a minimum end-of-life battery voltage of about 6v. however, analog common has some of the attributes of a reference voltage. when the total supply voltage is large enough to cause the zener to regulate (>7v), the common voltage will have a low voltage coefficient (0.001%/v), low output impedance ( ? 15 ? ), and a temperature coefficient typically less than 80ppm/ o c. the limitations of the on chip reference should also be recognized, however. with the icl7107, the internal heating which results from the le d drivers can cause some degradation in performance. d ue to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. the combination of reference temperature coefficient (tc), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25 v to 80 v p-p . also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. devices with a positive tc reference may require several counts to pull out of an over-range condition. this is because over-range is a low dissipation mode, with the three least significant digits blanked. similarly, units with a negative tc may cycle between over-range and a non-over- range count as the die alternately heats and cools. all these problems are of course eliminated if an external reference is used. the ICL7106, with its negligible dissipation, suffers from none of these problems. in either case, an external reference can easily be added, as shown in figure 4. analog common is also used as the input low return during auto-zero and de-integrate. if in lo is different from analog common, a common mode volt age exists in the system and is taken care of by the excellent cmrr of the converter. however, in some applications in lo will be set at a fixed known voltage (power supply common for instance). in this application, analog common should be tied to the same point, thus removing the common mode voltage from the converter. the same holds true for the reference voltage. if reference can be conveniently tied to analog common, it should be since this removes the common mode voltage from the reference system. within the lc, analog common is tied to an n-channel fet that can sink approximately 30ma of current to hold the voltage 2.8v below the positive supply (when a load is trying to pull the common line positive). however, there is only 10 a of source current, so common may easily be tied to a more negative voltage thus ove rriding the internal reference. figure 3. analog section of ICL7106 and icl7107 de - de+ c int c az r int buffer a-z int - + a-z comparator in hi common in lo 31 32 30 de- de+ int a-z 34 c ref + 36 ref hi c ref ref lo 35 a-z a-z 33 c ref - 28 29 27 to digital section a-z and de () integrator int stray stray v+ 10 a v- n input high 2.8v 6.2v v+ 1 input low - + - + - + figure 4a. ICL7106 v ref lo icl7107 ref hi v+ v- 6.8v zener i z ICL7106, icl7107, icl7107s
8 test the test pin serves two functions. on the ICL7106 it is coupled to the internally generated digital supply through a 500 ? resistor. thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the lcd display. figures 5 and 6 show such an application. no more than a 1ma load should be applied. the second function is a ?lamp test?. when test is pulled high (to v+) all segments will be turned on and the display should read ?1888?. the test pin will sink about 15ma under these conditions. caution: in the lamp test mode, the segments have a constant dc voltage (no square-wave). this may burn the lcd display if main- tained for extended periods. digital section figures 7 and 8 show the digital section for the ICL7106 and icl7107, respectively. in the ICL7106, an internal digital ground is generated from a 6v zener diode and a large p-channel source follower. this supply is made stiff to absorb the relative large capa citive currents when the back plane (bp) voltage is switched. the bp frequency is the clock frequency divided by 800. for three readings/sec., this is a 60hz square wave with a nominal amplitude of 5v. the segments are driven at the same frequency and amplitude and are in phase with bp when off, but out of phase when on. in all cases negligible dc voltage exists across the segments. figure 8 is the digital section of the icl7107. it is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminat ed and the segment drive has been increased from 2ma to 8ma, typical for instrument size common anode led displays. since the 1000 output (pin 19) must sink current from two led segments, it has twice the drive capability or 16ma. in both devices, the polarity indication is ?on? for negative analog inputs. if in lo and in hi are reversed, this indication can be reversed also, if desired. figure 4b. figure 4. using an external reference ICL7106 v ref hi ref lo common v+ icl8069 1.2v reference 6.8k ? 20k ? icl7107 ICL7106 v+ bp test 21 37 to lcd backplane to lcd decimal point 1m ? figure 5. simple inverter for fixed decimal point ICL7106 v+ bp test decimal point select cd4030 gnd v+ to lcd decimal points figure 6. exclusive ?or? ga te for decimal point drive ICL7106, icl7107, icl7107s
9 7 segment decode segment output 0.5ma 2ma internal digital ground typical segment output v+ lcd phase driver latch 7 segment decode 200 logic control internal v th = 1v 7 segment decode 1000?s 100?s 10?s 1?s to switch drivers from comparator output digital ground 4 clock 40 39 38 osc 1 osc 2 osc 3 backplane 21 v+ test v- 500 ? 37 26 6.2v counter counter counter counter 1 c a b c d f g e a b a b c d f g e a b c d f g e ? ? three inverters one inverter shown for clarity figure 7. ICL7106 digital section ICL7106, icl7107, icl7107s
10 system timing figure 9 shows the clocking arrangement used in the ICL7106 and icl7107. two basic clocking arrangements can be used: 1. figure 9a. an external oscillator connected to pin 40. 2. figure 9b. an r-c oscillator using all three pins. the oscillator frequency is divided by four before it clocks the decade counters. it is then further divided to form the three convert-cycle phases. t hese are signal integrate (1000 counts), reference de-int egrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). for signals less than full scale, auto-zero gets the unused portion of reference de-integrate. this makes a co mplete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. for three readings/second, an oscillator frequency of 48khz would be used. to achieve maximum rejection of 60hz pickup, the signal integrate cycle sh ould be a multiple of 60hz. oscillator frequencies of 240khz, 120khz, 80khz, 60khz, 48khz, 40khz, 33 1 / 3 khz, etc. should be selected. for 50hz rejection, oscillator frequencies of 200khz, 100khz, 66 2 / 3 khz, 50khz, 40khz, etc. would be suitable. note that 40khz (2.5 readings/second) wi ll reject both 50hz and 60hz (also 400hz and 440hz). 7 segment decode to segment 0.5ma 8ma digital ground typical segment output v+ latch 7 segment decode logic control 7 segment decode 1000?s 100?s 10?s 1?s to switch drivers from comparator output digital ground 4 clock 40 39 38 osc 1 osc 2 osc 3 v+ test 500 ? counter counter counter counter 1 v+ 37 27 c a b c d f g e a b a b c d f g e a b c d f g e ? ? three inverters one inverter shown for clarity figure 8. icl7107 digital section clock internal to part 40 39 38 gnd icl7107 4 clock internal to part 40 39 38 4 rc oscillator r c test ICL7106 figure 9b. figure 9. clock circuits figure 9a. ICL7106, icl7107, icl7107s
11 component value selection integrating resistor both the buffer amplifier and the integrator have a class a output stage with 100 a of quiescent current. they can supply 4 a of drive current with negligible nonlinearity. the integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requ irements are not placed on the pc board. for 2v full scale, 470k ? is near optimum and similarly a 47k ? for a 200mv scale. integrating capacitor the integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3v from either supply). in the ICL7106 or the icl7107, when the analog common is used as a re ference, a nominal +2v full- scale integrator swing is fine. for the icl7107 with +5v supplies and analog common tied to supply ground, a 3.5v to +4v swing is nominal. for three readings/second (48khz clock) nominal values for c lnt are 0.22 f and 0.10 f, respectively. of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. an additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. while other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. auto-zero capacitor the size of the auto-zero capacitor has some influence on the noise of the system. for 20 0mv full scale where noise is very important, a 0.47 f capacitor is recommended. on the 2v scale, a 0.047 f capacitor increa ses the speed of recovery from overload and is adequate for noise on this scale. reference capacitor a 0.1 f capacitor gives good results in most applications. however, where a large common mode voltage exists (i.e., the ref lo pin is not at analog common) and a 200mv scale is used, a larger value is required to prevent roll-over error. generally 1 f will hold the roll-over error to 0.5 count in this instance. oscillator components for all ranges of frequency a 100k ? resistor is recommended and the capacitor is selected from the equation: reference voltage the analog input required to gene rate full scale output (2000 counts) is: v ln = 2v ref . thus, for the 200mv and 2v scale, v ref should equal 100mv and 1v, respectively. however, in many applications where t he a/d is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. for instance, in a wei ghing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662v. instead of dividing the input down to 200mv, the designer should use the input voltage directly and select v ref = 0.341v. suitable values for integrating resistor and capacitor would be 120k ? and 0.22 f. t h i s makes the system slightly quieter and also avoids a divider network on the input. the icl7107 with 5v supplies can accept input signals up to 4v. another advantage of this system occurs when a digital reading of ze ro is desired for v in 0. temperature and weighi ng systems with a variable fare are examples. this offset reading can be conveniently generated by connecting the vo ltage transducer between in hi and common and the variable (or fixed) offset voltage between common and in lo. icl7107 power supplies the icl7107 is designed to work from 5v supplies. however, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lc. figure 10 shows this application. see icl7660 data sheet for an alternative. in fact, in selected applications no negative supply is required. the conditions to use a single +5v supply are: 1. the input signal can be referenced to the center of the common mode range of the converter. 2. the signal is less than 1.5v. 3. an external reference is used. f 0.45 rc ----------- for 48khz clock (3 readings/sec), = c 100pf. = icl7107 v+ osc 1 v- osc 2 osc 3 gnd v+ v- = 3.3v 0.047 f 10 f + - 1n914 1n914 cd4009 figure 10. generating negative supply from +5v ICL7106, icl7107, icl7107s
12 typical applications the ICL7106 and icl7107 may be used in a wide variety of configurations. the circuits which follow show some of the possibilities, and serve to illust rate the exceptional versatility of these a/d converters. the following application not es contain very useful information on understanding and applying this part and are available from intersil corporation. application notes note # description an016 ?selecting a/d converters? an017 ?the integrating a/d converter? an018 ?do?s and don?ts of applying a/d converters? an023 ?low cost digital panel meter designs? an032 ?understanding the auto-zero and common mode performance of the icl7136/7/9 family? an046 ?building a battery-operated auto ranging dvm with the ICL7106? an052 ?tips for using single chip 3 1 / 2 digit a/d converters? an9609 ?overcoming common m ode range issues when using intersil integrating converters? typical applications figure 11. ICL7106 using the internal reference figure 12. icl7107 using the internal reference 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 100pf to pin 1 set v ref = 100mv 0.1 f 0.01 f 1m ? 100k ? 1k ? 22k ? in + - 9v 47k ? 0.22 f 0.47 f to backplane to display values shown are for 200mv full scale, 3 readings/sec., floating supply voltage (9v battery). + - values shown are for 200mv full scale, 3 readings/sec. in lo may be tied to either common for i nputs floating with respect to supplies, or gnd for single ended inputs. (see discussion unde r a nalog common). 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 f 0.01 f 1m ? 100k ? 1k ? 22k ? in + - 47k ? 0.22 f 0.47 f to display +5v -5v ICL7106, icl7107, icl7107s
13 figure 13. icl7107 with an external band-gap reference (1.2v type) figure 14. icl7107 with zener diode reference figure 15. ICL7106 and icl7107: recommended component values for 2v full scale figure 16. icl7107 operated from single +5v typical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 f 0.01 f 1m ? 100k ? 1k ? 10k ? in + 47k ? 0.47 f to display in lo is tied to supply common es tablishing the correct common mode voltage. if common is not shorted to gnd, the input voltage may floa t with respect to the power supply and common acts as a pre-regulato r for the reference. if common is s horted to gnd, the input is single ended (referred to supply gnd) and the pre-regulator is overridden. 10k ? 1.2v (icl8069) v - v + - 0.22 f since low tc zeners have breakdown voltages ~ 6.8v, diode must be placed across the total supply (10v ). as in the case of figure 12, in lo may be tied to either common or gnd. 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 f 0.01 f 1m ? 100k ? 1k ? 100k ? in + - 47k ? 0.22 f 0.47 f to display +5v -5v 6.8v 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp/gnd 100pf to pin 1 set v ref = 1v 0.1 f 0.01 f 1m ? 100k ? 25k ? 24k ? in + - 470k ? 0.22 f 0.047 f to display v+ v- 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 set v ref = 100mv 0.1 f 0.01 f 1m ? 100k ? 1k ? 10k ? in + - 47k ? 0.22 f 0.47 f to display a n external reference must be used in this application, since the voltage between v+ and v- is insufficient for correct operation of the internal reference. 15k ? 1.2v (icl8069) +5v ICL7106, icl7107, icl7107s
14 figure 17. icl7107 measureing ratiometric values of quad load cell figure 18. ICL7106 used as a digital centigrade thermometer figure 19. circuit for developing underrange and overrange signal from ICL7106 outputs figure 20. circuit for developing underrange and overrange signals from icl7107 output typical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 gnd 100pf to pin 1 0.1 f 100k ? 0.47 f to display the resistor values within the bridge are determined by the desired sensitivity. v+ 0.22 f 47k ? 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 100pf to pin 1 0.1 f 0.01 f 100k ? 100k ? 1m ? 9v 47k ? 0.22 f 0.47 f to backplane to display a silicon diode-connected transistor has a temperature coefficient o f about -2mv/ o c. calibration is achiev ed by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. the sensor shoul d then be placed in boiling wate r and the scale-factor potentiometer adjusted for a 100.0 reading. scale factor adjust 100k ? 220k ? 22k ? silicon npn mps 3704 or similar zero adjust 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp o/range u/range cd4023 or 74c10 cd4077 to logic v cc v+ to logic v- gnd o/range u/range cd4023 or 74c10 to logic v cc +5v v- 33k ? the lm339 is required to ensure logic compatibility with heavy display loading. 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v- g2 c3 a3 g3 bp 12k ? + - + - + - + - lm339 ICL7106, icl7107, icl7107s
15 figure 21. ac to dc converter with ICL7106 figure 22. display buffering for increased drive current typical applications (continued) 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref c ref common in hi in lo a-z buff int v - g2 c3 a3 g3 bp 100pf to pin 1 0.1 f 100k ? 1k ? 22k ? 47k ? 0.22 f 0.47 f to backplane to display test is used as a common-mode reference level to ensure compatibility with most op amps. 10 f 9v 10 f 470k ? 1 f 4.3k ? 100pf (for optimum bandwidth) 1 f 10k ? 10k ? 1n914 1 f 0.22 f 5 f ca3140 2.2m ? + - 100k ? ac in scale factor adjust (v ref = 100mv for ac to rms) + - icl7107 130 ? 130 ? 130 ? led segments +5v dm7407 ICL7106, icl7107, icl7107s
16 ICL7106, icl7107, icl7107s dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e40.6 (jedec ms-011-ac issue b) 40 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.980 2.095 50.3 53.2 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n40 409 rev. 0 12/93
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ICL7106, icl7107, icl7107s metric plastic quad flatpack packages (mqfp) d d1 e e1 -a- pin 1 a2 a1 a 12 o -16 o 12 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.076 0.003 -c- -d- -h- q44.10x10 (jedec ms-022ab issue b) 44 lead metric plastic quad flatpack package symbol inches millimeters notes min max min max a - 0.096 - 2.45 - a1 0.004 0.010 0.10 0.25 - a2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.515 0.524 13.08 13.32 3 d1 0.389 0.399 9.88 10.12 4, 5 e 0.516 0.523 13.10 13.30 3 e1 0.390 0.398 9.90 10.10 4, 5 l 0.029 0.040 0.73 1.03 - n44 447 e 0.032 bsc 0.80 bsc - rev. 2 4/99 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toleranc es per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. ?n? is the number of terminal positions. -c- -h-

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